Asian Test Symposium 2011: Part II

We reached the venue called Hotel Crowne Plaza in Okhla. The place looked a bit odd. Okhla is an industrial area and polluted. You get the smell of industries as soon as you enter Okhla. I wish it was a hotel somewhere near Connaught Place in New Delhi. Perhaps those places were too expensive f or the organizers. I was not too impressed with Crowne Plaza and Okhla.

I met Janusz Rajski at the registration desk. He is Chief Scientist and Director of Engineering at Mentor's ATPG and EDT division. I work with Synopsys which is a competitor of Mentor. But I must confess that I'm a great fan of Janusz because of his singular contribution to Test. Pramod and I introduced ourselves to Janusz. I told him that I met him last time during ITC 2008 when Rohit (my manager Rohit Kapur) introduced me to him. Janusz exactly remembered the place where we met in ITC 2008. He told me that it was during the poster-session of ITC 2008 when Rohit introduced me! I was completely taken aback by his strong memory.

Inside the conference hall, I met many of my old friends from Cadence there. Exchanged pleasantries with all of them.

The Organizing Committee co-Chairs Prof Patra from IITKgp started ATS with his welcome note. It was followed by two keynote speeches. The first keynote speech was by Prof Giovanni De Micheli  of EPFL and the second keynote speaker was Janusz Rajski from Mentor.

Prof Giovanni is a renowned Synthesis expert, His book on Synthesis is considered as the most important text book on Synthesis.  I was very happy to see him in person.  But as he started his speech and moved towards the middle of the speech, I realized that perhaps he is not best fit as a keynote speaker on Test. He would be perfectly good on DAC; but perhaps a bit misfit for the keynote role in ATS.

Janusz started his keynote on Future of Test from EDA and Design perspetive. The topic was very interesting. Janusz is one of the renowned Test gurus in the world. I wanted him to take an industry  visonary role today and was hoping that he would not be just trying to Mentor's Test. Janusz started with a difference. He asked most of the lights in the hall to be switched off. He said people who are jet-lagged could take some rest also.  He used a background which he said resembled like nano-tubes. First he showed all pictures of himself and his family on some mountaineering trips. It was kinda irrevelant. But you know he is a big guy and you need to appreciate anything good or bad from people like him. After multiple pictures, he went to the outline of his presentation.

Janusz emphasized the importance of Scan Compression. He showed some of the most influential papers published in Compression till now. He chose to ignore Adaptive Scan (Synopsys DFTMAX) in that list of papers. He showed his own EDT paper of ITC 2001, Survey of Compression by Nur Touba, and one more paper from Cadence folks on OPMISR.  I was surprised to see DFTMAX being ignored here. Mentor and Synopsys almost dominate Test; Cadence is a relatively minor player in Test. I was a bit skeptical at that point if Janus was wearing the cap of a visionary in Test or just the cap of Mentor! He then mentioned something important which kinda gave a reason for exclusion of DFTMAX.  He said any (compression) technology that has endured for 10 years is worth a technology to be mentioned as path-breaking in that slide. I may be wrong in th exact words that he used for this sentence; but this was the essence of his statement!

Janusz also mentioned one very important thing about Scan Compression. He said that any Compression solution which does not work like the pure Scan is not useful. He showed some of his slides from his keynote speech in ATS 2001 in Kyoto and ATS 2005 in Calcutta where predicted that the future of Test was Scan Compression. He said now he felt proud that he could foresee the future. At this point, I had a question for him which I asked him later during Q&A.

Janusz told about two technologies that he believed would be the future of Test going forward. One was hierarchical based DFT and the other was a hyrid of Scan Compression and BIST. The first is definitely true and no one in Test can deny that. I am a bit doubtful about the second. Mentor bought LogicVision sometime back and got the BIST technology. BIST is an old technology and it preceds Scan Compression.But BIST was never completely adopted by the design community in the way Compression found the widespread acceptance. Then will a hybrid of Scan Compression and BIST will be useful and successful? Janusz emphasized this point again when he concluded his speech.

Then time came for Q&A. The program was running about 15 minutes late. So Ravi Srivaths, one of the co-chairs of the organizing committee told that only two questions be permitted. I stood first and luckily there was a girl from Crowne Plaza hotel standing with a mic near me. So I got the opportnity to ask Janus  aquestion. Janus showed some slides from his ATS 2001 presentation today. On that context, I asked him which one or two slides from his today's presentation that he thought he could present in ATS 2021 if he is invited to give a keynote in ten years from now. He first didn't understsand my question. I think Ravi explained him my question. Janusz said that he ddn't want to feel accountable for something; but it was a good question. He went on explaining the virtues of hiearchical DFT and hybrid solution of Compression and BIST. He said he hoped these two woulo be the future.

Then the paper presentation session started. I attended the session on Timing and Clock which my colleague Pramod was moderating. All the four papers in this session was presented by four professors and three of them are quite renowned. First one was a profesor from Japan on Testing Transition delay faults in Clock. The next three papers were presented by Prof Krishnenu Chakrabarty of Duke, Prof Jacob Abraham of Texas, Austin and Prof Abhijit Chatterjee of Georgia Tech. It was very good to see these people presenting. Prof Krish Chakrabarty was the PhD advisor of my colleague Anshuman Chandra. Later I had a good conversation with Prof Chakrabarty. Pramod did an excellent job of charing the session. He was very planned and neat. He collected the bios of the all the presenters beforehand and introduced them well. He also collected the abstract of their papers in case he had to ask some questions to them.

Lunch was good; but I ate a light one because I had to present a paper immediately after lunch. My session was to be chaired by a professor from Japan. He didn't collect my bio or anything. He just took my business card and introduced me from the card.

As I went to the podium, I was a bit nervous on the title slide. But very soon I regained my confidence and was able to explain the stuffs pretty well. In the audience, there were many familiar faces - Rohit, Pramod and many of my ex-colleagues from Cadence.

Asian Test Symposium 2011: Part I

It all started with an email that Prof Abhijit Chatterjee from Georgia Tech sent to my manager Rohit Kapur in the first week of February stating that he wanted to meet with the Test people in Synopsys Bangalore. Prof Chatterjee was going to be the General Chair of ATS 2011 to be held in Delhi in November. He was trying to meet the people from academic and industry in India in order to drum up support for the conference.

There are four  Test conferences that happen annually - ITC, VTS, ETS and ATS. International Test Conference (ITC) is the most premier conference of all these. I think next comes VLSI Test Symposium (VTS). Both ITC and VTS happen in US. European Test Symposium (ETS) and Asian Test Symposium (ATS) rotate amongst countries in Europe and Asia respectively. ATS usually comes to India once in every decade. ATS 2011 would be 20th ATS.

Prof Chatterjee came to meet us on February 10th in our Synopsys Bangalore office. He was accompanied by Prof Viren Singh of IISc. My friend and colleague Parthajit and I met them for some time where they explained us about the Test Oddysey theme for this ATS. We then took them to lunch at Indijoes at RMZ Infinity.

We submitted two papers to the conference. Both of these were already filed as US patents in USPTO. One was on the concept of Predicting Test Compression QoR and the other one was on something called Cyclical Adaptive Scan (CAS). Both the papers were accepted. So I got the opportunity to travel.I'd be presenting the Compression Maximizer paper. My colleague Pramod was invited to be a moderator for one of the sessions. So both of us would travel from Synopsys Bangalore to attend ATS in Delhi.

But there was a bit of a problem. We were expecting our second baby and Gitika's expected date of delivery (EDD) was Dec 14th. We had some buffers so that I could go and present the paper in ATS. I was still a bit hesitant. As usual, Gitika is one of the brave ladies I've ever met. If I would have been in her place, I would have never let my spouse to travel in such a crucial time.But Gitika was exactly opposite. She was encouraging me to attend ATS and present the paper. One day Rohit called me and spoke to Gitika about my travel. She told Rohit also that I should travel.

Gitika's sugar level was high. So her gynecologist told us that we won't wait till EDD. Finally we planned Novemver 25th as her day for c-sec. I'd come back to Bangalore after the end of the last day of ATS on Nov 23rd and get her admitted on Nov 24th night.

But something different was waiting for me..

I landed in Delhi on Nov 20th, Sunday, one day ahead of ATS in order to meet my old friends in Noida. I visited Utpal da's family and had lunch there. After that, I went to meet my ex-colleague and friend Subhasish. He has newly constructed a beautiful house in Noida. Utpal da dropped us at our C.R. Park hotel later in the evening.

4 years in Synopsys

I completed 4 years in the same job today. I joined Synopsys in September, 2007 and has been working there since then. My previous best was 2 year 10 months at Cadence - from December 2004 to September 2007. In the period before joining Cadence, I worked in three different companies in three years! So considering my previous work history, 4 years in a single company is definitely a record. :-)

Well, I like my current job and hope to play a long innings here.

From EDA to drug-discovery!

Some EDA veterans are using the skills they developed in EDA to simulate the behavior of therapeutics. Sounds cool; isn't it? The company is CellWorks Group. They are in stealth mode and their website doesn't reveal anything about what they are doing now.

CellWorks Group is founded by two of my ex-colleagues from Cadence - Pradeep Fernandes and Taher Abbasi. Pradeep was the Business Unit head of RTL Compiler (RC) synthesis and Taher was the Director for Field Operations for RC. Then CWG's India Managing Director is Anand Anandkumar who was Magma India's MD before joining CWG. Pradeep, Taher, Anand etc are all EDA veterans.

Anand's linked-in profile mentions CWG as an extremely exciting and hot startup  which is in the area of Pharma therapeutics, using a novel principle called Virtual Proteomics. This company has the opportunity to revolutionize how drugs (particularly combination therapies) will be designed and brought to market.

Pradeep's linked-in profile reveals this about CWG: CWG is creating a comprehensive library of disease platforms. These platforms enable the predictive analysis of drug-disease interaction in-silco. This predictive analysis enables safer and more potent drugs to be designed in a shorter time, by enabling fast-failing and fast-scaling methodologies.

CellWorks started an India R&D center in bangalore in 2007. This news reveals some more information about CWG:

1. CellWork Research India Limited (CRIL)’s research focus would be in the areas of oncology, inflammation, metabolic disorders, CNS and Skin.
2. Their research is based on Systems Biology approach.
3. It involves development of in silico platforms of disease physiology at the metabolic and bio-chemical pathway level
4. The in-silico approach enables drug discovery teams to use these platforms as a virtual experimental system.
5. The drug discovery teams would have the benefit of using the in silico system in conjunction with currently used in vitro and in vivo techniques.

Why am I so excited about this news? There are two reasons:

1. I'm happy to see the EDA knowledge being applied in Bio-Medical research. We actually do cool stuffs in EDA :-).
2. I always feel that mankind should have overcome killer deseases like cancer by now. But the reality is that we're still not able to prevent and cure cancer completely. I look for the day when there will be some vaccines against cancer. I hope efforts like CWG will bring us closer to that day when we shall overcome cancer.

Future of EDA

Recently I've read two interesting articles written on future of EDA industry. It's predicted that by 2017 semiconductor industry will grow to become a US$1 trillion industry. Currently it's about US$270 billion. It's predicted that EDA industry will reach US$10 billion market in next 10 years. Here is the full article titled Future challenges for the EDA industry: A business perspective http://www.edn.com/article/CA6711232.html. The author of the article is S.N. Pamanabhan who is a Senior VP of R&D Services at MindTree.

The second article that I read recently is titled EDA: Aging or Dying. It was published in EE Times 10/02/2010 and written by Mike Gianfagna, Vice President marketing at Atrenta Inc. It states that EDA is maturing, not dying.

EDA: Looking for new avenues?

In February 2010, there are five events that indicate that EDA industry has started looking beyond its core areas of EDA and IP. These events are listed below in some random order:

1. On 18th February at a panel discussion during EDA Consortium (EDAC)'s Annual CEO Forecast and Industry Vision event, all the CEOs agreed that there is a need to explore new market segments. At the same time, they cautioned that new segments require sustained effort and considerable patience. The related news from EE Times is here.
2. Synopsys, the largest EDA company, acquired virtual system prototyping technology provider Vast Systems Technology Corp on 2nd February. Here is the news from EE Times.
3. Synopsys signed a definitive agreement to buy electronic system-level (ESL) design software vendor Coware Inc on February 8th. Here is the EE Times news.
4. Mentor Graphics, the third largest EDA company, acquired the Virtual Garage software suite from Freescale Semiconductor Inc. to expand electrical design scope. Here is the news from EE Times.
5. Mentor Graphics, on 16th February, announced it has named Serge Leef, current general manager of the System Level Engineering division, as Vice President of New Ventures. His role will be to expand the company into markets adjacent to EDA. The related news from EE Times is here.

Looks like EDA is looking into embedded/system level design for new growth opportunities. EDA industry is almost stuck at a US$4 billion market for past several years.

EDA-I: what is EDA?

I work in the EDA industry. It's a very small and niche sector. The total EDA revenue is about US$ 4 billion. There are four major players here: Synopsys, Cadence, Mentor Graphics and Magma. Besides these, there are many small companies specializing in some nicher area of EDA. Examples of some these smaller companies are: Atrenta (focussing on early design closure), SequenceDesign (focussing on low power and Parasitic Extraction), Calypto, Denali, NuSym, Synfora etc. Here is one long list of EDA companies:
http://en.wikipedia.org/wiki/List_of_EDA_companies

Many of my friends work in the IT industry. But most of them are ignorant of EDA. Almost every one of them has different notion on what I do. Some of them think that I'm into DSP. Some other guy thinks that I work in the hardware design. Someone thinks that I work in the embedded software domain. Then I've another friend who thinks that I'm into firmware development.

I have another category of friends who are aware of EDA; but they just don't know what we do in EDA. They think I write Verilog or VHDL code. They ask me: what is the input to my tool and what is its output.

Then someone came to know that I work in VLSI Test in EDA. Since Testing in the software industry is called QA (Quality Assurance), some of my friends believe that I do some kind of QA work!

I plan to write a series of articles here on what we do in EDA industry. I'll write it in a very simple language.

First of all, EDA stands for Electronic Design Automation. We're VLSI CAD guys. Many people know about AutoCAD : the CAD tool for mechanical design. EDA plays a similar role for semiconductor design & manufacturing.

If you're a civil engineer designing and constructing bridges, you don't start building the bridge right away when you get the assignment. You first design it in a software, simulate it, analyze various engineering aspects of it. You deal with a model of the bridge during the design phase. A model might be a software model, a mathematical model (truss etc), or just a design that you drew with a pencil. Once you finalize the design, then the construction of the bridge starts. Same is the case with a mechanical engineer working in an automobile industry. When a new car is to be launched, the automobile company just doesn't start manufacturing the car. The design engineer will first model the car in a software and take it through all the phases of the design.

EDA plays the similar role for electronic design. EDA industry creates CAD tools for electronic design engineers (both chip and board). They take a chip from design to manufacturing using various EDA tools.

There are two large forums for EDA folks:

1. CEDA (IEEE Council on Electronic Design Automation)
2. SIGDA (ACM Special Interest Group on Design Automation)
   

I think the biggest conference (and broadest - covering all aspects of EDA) in EDA industry is DAC (Design Automation Conference). DAC might possibly be the oldest conference also in EDA industry. Its 46th conference will be held in July 2009. (DAC is 46 year old whereas EDA as an industry is probably in its twenties now!)

Is there any person who can be called as father of EDA? IMHO, Prof Alberto Sangiovanni-Vincentelli of EECS department of Berkley definitely fits into that role. He was a co-founder of Synopsys and Cadence, the two leading companies in the area of EDA. He was a Director of ViewLogic and Chair of the Technical Advisory Board of Synopsys. He is the Chief Technology Advisor of Cadence Design System. His paper Tides of EDA explains the evolution of the EDA industry.

There is a power-point presentation on EDA titled EDA-story-so-far that also explains the EDA industry nicely.

In my next post, I'll describe how we can categorize different EDA tools (Implementation, Verification, Frontend, Backend, ASIC/FPGA/SoC, PCB/SiP, IP, Design Services etc. Strictly speaking, IPs are not tools, but small designs. More about that in my next post.)